1. Field of the Invention
This invention relates-to a process for producing a semiconductor article that can suitably be used for producing a semiconductor device such as a semiconductor integrated circuit, a solar cell, a semiconductor laser device or a light emitting diode. More particularly, it relates to a process for producing a semiconductor article including a step of separating a substrate.
2. Related Background Art
Semiconductor articles are popular in terms of semiconductor wafers, semiconductor substrates and various semiconductor devices and include those adapted for producing semiconductor devices by utilizing the semiconductor region thereof and those used as preforms for producing semiconductor devices.
Some semiconductor articles of the type under consideration comprise a semiconductor layer arranged on an insulator.
The technology of forming a single crystal silicon semiconductor layer on an insulator is referred to as silicon on insulator (SOI) technology, which is widely known. Various research has been done to exploit the remarkable advantages of SOI that cannot be achieved by using bulk Si substrates that are used for producing ordinary Si integrated circuits. The advantages of the SOI technology include:
1. The ease of dielectric isolation that allows an enhanced degree of integration; PA1 2. The excellent resistivity against radiation; PA1 3. A reduced floating capacitance that allows a high device operation speed; PA1 4. The omission of the well forming step; PA1 5. The effect of latch up prevention; and PA1 6. The possibility of producing fully depleted field effect transistors using the thin film technology. The advantages of the SOI technology are thoroughly discussed in Special Issue: "Single-crystal silicon on non-single-crystal insulators"; edited by G. W. Cullen, Journal of Crystal Growth, volume 63, No. 3, pp. 429-590 (1983). PA1 (1) polishing, PA1 (2) local plasma etching, and PA1 (3) selective etching.
In recent years, a number of reports have been published on the SOI technology for providing substrates that can realize high speed operation and low power consumption for MOSFETs (IEEE SOI conference 1994). The process of manufacturing a semiconductor device can be significantly enhanced by using the SOI structure when compared with the corresponding process of manufacturing a device on a bulk Si wafer, because of the implementation of a very simplified device isolation step. Thus, the use of the SOI technology can provide a significant cost reduction in manufacturing a semiconductor device, particularly in terms of the wafer cost and the process cost if viewed from the conventional technology of manufacturing a MOSFET or an IC on a bulk Si substrate, to say nothing of the remarkable performance of such a semiconductor device.
Fully depleted MOSFETs are very promising for achieving high speed operation and low power consumption if provided with improved drive power. Generally speaking, the threshold voltage (Vth) of a MOSFET is determined as a function of the impurity concentration of its channel section but, in the case of a fully depleted (FD) MOSFET, the characteristics of the depletion layer are influenced by the SOI film thickness. Therefore, the SOI film thickness has to be rigorously controlled in order to improve the yield of manufacturing LSIs.
Meanwhile, a device formed on a compound semiconductor shows a remarkable level of performance that cannot be expected from silicon, particularly in terms of high speed operation and light emission. Such devices are currently formed by means of epitaxial growth on a compound semiconductor substrate that may be made of GaAs or a similar compound. However, a compound semiconductor substrate is costly and mechanically not very strong so that it is not adapted to produce a large wafer.
Thus, efforts have been made to form a compound substrate by hetero-epitaxial growth on a Si wafer that is inexpensive, mechanically strong and good for producing a large wafer.
Research on forming SOI substrates became significant in the 1970s. Initially, attention was paid to the technique of producing single crystal silicon by epitaxial growth on a sapphire substrate (SOS: silicon on sapphire), that of producing a SOI structure through full isolation by porous oxidized silicon (FIPOS) and the oxygen ion implantation technique. The FIPOS method comprises steps of forming an island of N-type Si layer on a P-type single crystal Si substrate by proton/ion implantation (Imai et al., J. Crystal Growth, Vol. 63,547 (1983)) or by epitaxial growth and patterning, transforming only the P-type Si substrate into a porous substrate by anodization in a HF solution, shielding the Si islands from the surface, and then subjecting the N-type Si islands to dielectric isolation by accelerated oxidation. This technique is, however, accompanied by a problem that the isolated Si region is defined before the devices are produced and restricts the freedom of device design.
The oxygen ion implantation method is also referred as the SIMOX method, which was proposed by K. Izumi for the first time. With this technique, oxygen ions are implanted into a Si wafer to a concentration level of 10.sup.17 to 10.sup.18 /cm.sup.2 and then the latter is annealed at high temperature of about 1,320.degree. C. in an argon/oxygen atmosphere. As a result, the implanted oxygen ions are chemically combined with Si atoms to produce a silicon oxide layer that is centered at a depth corresponding to the projection range (Rp) of the implanted ions. Under this condition, an upper portion of the Si oxide layer that is turned into an amorphous state by the oxygen ion implantation is recrystallized to produce a single crystal Si layer. While the surface Si layer used to show a defect rate as high as 10.sup.5 /cm.sup.2, a recent technological development has made it possible to reduce the defect rate down to about 10.sup.2 /cm.sup.2 by selecting a rate of oxygen implantation of about 4.times.10.sup.17 /cm.sup.2. However, the allowable range of energy infusion and that of ion implantation are limited if the film quality of the Si oxide layer and the crystallinity of the surface Si layer are to be held to respective desired levels. Hence the film thickness of the surface Si layer and that of the buried Si oxide (BOX; buried oxide) layer are allowed to take only limited values. In other words, a process of sacrificial oxidation or epitaxial growth is indispensable to realize a surface Si layer having a desired film thickness. Such a process by turn gives rise to a problem of uneven film thickness due to the intrinsic adverse effect of the process.
There have been reports saying that SIMOX can produce defective Si oxide regions in the Si oxide layer that are referred to as pipes. One of the possible causes of the phenomenon may be foreign objects such as dust introduced into the layer at the time of ion implantation. The device produced in a pipe region can show degraded characteristics due to the leak current between the active layer and the underlying substrate.
The SIMOX technique involves the use of a large volume of ions that is by far greater than the volume used in the ordinary semiconductor process and hence the ion implantation process may take a long time if a specifically designed apparatus is used for it. Since the ion implantation process is performed typically by raster scanning of an ion beam showing a predetermined flow rate of electric current or by spreading an ion beam, a long time may be required for processing a large wafer. Additionally, when a large wafer is processed at high temperature, the slip problem due to an uneven temperature distribution within the wafer can become very serious. Since the SIMOX process requires the use of extraordinary high temperature that is as high as 1,320.degree. C., which is not observed in the ordinary Si semiconductor process, the problem of uneven temperature distribution will become more serious if a large wafer has to be prepared, unless a highly effective apparatus is not realized.
Beside the above described known techniques of forming SOI, a technique of bonding a single crystal Si substrate to another single crystal Si substrate that has been thermally oxized to produce an SOI structure has been proposed recently. This method requires the use of an active layer having an even thickness for the devices to be formed on it. More specifically, a single crystal Si substrate that is as thick as several hundreds micrometers has to be made as thin as several micrometers or less. Three techniques have been known for thinning a single crystal Si layer that include;
It is difficult to achieve an even film thickness by means of the polishing technique above. Particularly, the mean deviation in the film thickness can be as large as tens of several percent to make the technique unfeasible when the film is thinned to an order of sub-micrometer. This problem will become more significant for wafers having a large diameter.
The technique of local plasma etching is typically used in combination with that of polishing. More specifically, the film is thinned by means of the technique of polishing to about 1 to 3.mu.m, and the distribution of film thickness is determined by observing the film thickness at a number of points. Then, the film is subjected to an etching operation where the film is scanned with a plasma of SF.sub.6 particles having a diameter of several millimeters, and correcting the distribution of film thickness until a desired film thickness is obtained. There has been a report that the distribution of film thickness can be confined within about .+-.10 nm or less by means of this technique. However, this process is accompanied by a drawback that, if foreign objects are present on the substrate in the form of particles during the plasma etching, they operate as so many etching masks to produce projections on the substrate when the etching operation is over.
Additionally, since the substrate shows a coarse surface immediately after the etching operation, a touch-polishing operation has to be conducted on the surface after the end of the plasma etching and the operation is controlled only in terms of its duration. Then, again the problem of deviations in the film thickness due to polishing arises. Still additionally, a polishing agent typically containing colloidal silica is used for the polishing operation. Hence the layer for making an active layer is directly scraped by the polishing agent so that a crushed and/or distorted layer may be produced. The throughput of the process can be significantly reduced when large wafers are treated because the duration of the plasma etching operation is prolonged as a function of the surface area of the wafer being processed.
The technique of (3) involves the use of a film configuration for the substrate to be thinned that comprises one, or more than one, film layers adapted to selective etching. For example, assume that a P.sup.+ -Si thin layer containing boron by more than 10.sup.19 /cm.sup.3 and a P-type Si thin layer are made to grow sequentially on a P-type substrate by means of epitaxial growth to produce a first substrate, which is then bonded to a second substrate with an insulation layer interposed therebetween, the insulation layer being typically an oxide film, and that the rear surface of the first substrate is made sufficiently thin in advance by scraping and polishing. Subsequently, the P.sup.+ -layer is exposed by selectively etching the overlying P-type layer and then the P-type substrate is exposed by selectively etching the P.sup.+ -layer, to produce an SOI structure. This technique is discussed in detail in a report by Maszara (W. P. Maszara, J. Electrochem. Soc., Vol. 138,341 (1991)).
While the selective etching technique is effective for producing a thin film with an even film thickness, it is accompanied by the drawbacks as identified below.
The selective etching ratio is not satisfactory and will be as low as 10.sup.2 at most.
A touch-polishing operation is required to smooth the surface after the etching operation because of the coarse surface produced by the etching operation. Therefore, the film thickness can lose the uniformity as it is reduced by polishing. Particularly, while the polishing operation is controlled by the duration of the operation, it is difficult to rigorously control the operation because the polishing rate can vary significantly from time to time. Thus, this problem becomes significant when forming an extremely thin SOI layer that is as thin as 100 nm.
The resulting SOI layer can show a poor crystallinity due to the use of a film forming technique that involve ion implantation and epitaxial or hetero-epitaxial growth on a Si layer that is densely doped with B. Additionally, the bonded surface of the substrate may show a degree of smoothness that is inferior relative to that of a conventional Si wafer (C. Harendt, et al., J. Elect. Mater. Vol. 20,267 (1991), H. Baumgart, et al., Extended Abstract of ECS first International Symposium of Wafer Bonding, pp-733 (1991), C. E. Hunt, Extended Abstract of ECS first International Symposium of Wafer Bonding, pp-696 (1991)). Still additionally, there is a problem that the selectivity of the selective etching technique heavily depends on the concentration difference among the impurities such as boron contained in the substrate and the steepness of the concentration profile of the impurities along the depth of the substrate. Therefore, if the bonding annealing is conducted at high temperature to improve the bonding strength of the layers, and the epitaxial growth is carried out also at high temperature to enhance the crystallinity of the SOI layer, the concentration profile of the impurities along the depth becomes flattened to reduce the selectivity of the etching operation. Simply stated, the improvement of the etching selectivity, and hence that of the crystallinity, and the improvement of the bonding strength are conflicting requirements that cannot be met at the same time.
Under these circumstances, the inventors of the present invention proposed a novel method of manufacturing a semiconductor article in Japanese Patent Application Laid-Open No. 5-21338. According to the invention, the proposed method is characterized by forming an article by arranging a nonporous single crystal semiconductor region on a porous single crystal semiconductor region, bonding the surface of a material carrying an insulating material thereon to the corresponding surface of said porous single crystal semiconductor region and subsequently removing said porous single crystal semiconductor region by etching.
T. Yonehara et al. who are the inventors of the present invention also reported a bonded SOI that is excellent in terms of even film thickness and crystallinity and adapted to batch processing (T. Yonehara et al., Appl. Phys. Lett. Vol. 64, 2108 (1994)). The proposed method of manufacturing a bonded SOI will be summarily described below by referring to FIGS. 16A through 16C of the accompanying drawings.
The proposed method uses a porous layer 902 formed on a first Si substrate 901 as a layer to be selectively etched. After forming a nonporous single crystal Si layer 903 on the porous layer 902 by epitaxial growth, it is bonded to a second substrate 904 with a Si oxide layer 905 interposed therebetween (FIG. 16A). Then, the porous Si layer is exposed over the entire surface area of the first substrate by scraping off the first substrate from the rear side (FIG. 16B). The exposed porous Si is then etched out by means of a selective etching solution typically containing KOH or HF+H.sub.2 O.sub.2 (FIG. 16C). Since the selective etching ratio of the operation of etching the porous Si layer relative to the bulk Si layer (nonporous single crystal Si layer) can be made as high as hundreds of thousands with this technique, the nonporous single crystal Si layer formed on the porous layer in advance can be transferred onto the second substrate to produce a SOI substrate without reducing the thickness of the nonporous single crystal Si layer. Thus, the uniformity of the film thickness of the SOI substrate is determined during the epitaxial growth step. According to a report by Sato et al., since a CVD system adapted to an ordinary semiconductor process can be used for the epitaxial growth, a degree of uniformity of the film thickness as high as 100 nm .+-.2% can be realized. Additionally, the epitaxial Si layer shows an excellent crystallinity of about 3.5.times.10.sup.2 /cm.sup.2.
Since the selectivity of any conventional selective etching technique heavily depends on the concentration difference among the impurities contained in the substrate and the steepness of the concentration profile of the impurities along the depth of the substrate as described above, the temperature of the heat treatment (for bonding, epitaxial growth, oxidation and so on) is limited to as low as 800.degree. C. at most because the impurity concentration profile becomes flattened above that temperature limit. On the other hand, the etching rate of the proposed etching technique is mainly determined by the structural difference between the porous layer and the bulk layer so that the heat treatment is not subjected to such a rigorous limitation and temperature as high as 1,180.degree. C. can be used. It is known that a heat treatment process conducted after the bonding operation can remarkably improve the bonding strength between wafers and reduce the size and number of voids given rise to on the bonding interface. Additionally, with a selective etching operation relying on the structural difference between the porous layer and the bulk layer, the uniformity of the film thickness is not adversely affected by fine particles that can be adhering to the porous Si layer.
However, a semiconductor substrate to be produced by way of a bonding process inevitably requires at least two wafers as starting materials, one of which is substantially wasted away in the course of polishing and etching to consume the limited natural resources. In other words, a SOI manufacturing process is required to realize low cost and economic feasibility in addition to an enhanced degree of process controllability and an improved uniformity of the film thickness.
Differently stated, the requirements of a process for manufacturing a high quality SOI substrate include an excellent reproducibility, an enhanced level of resource saving capability through the repeated use of a same wafer and low manufacturing cost.
Under such circumstances, the inventors of the present invention disclosed, in Japanese Patent Application Laid-Open No. 7-302889, a process for producing a semiconductor substrate in which two substrates are bonded together and the bonded substrates are separated at the porous layer and the separated one substrate is reused after eliminating the remaining porous layer. An example of this process is explained by reference to FIGS. 17A to 17C.
A surface layer of a first Si substrate 1001 is made porous to form porous layer 1002, and single crystal Si layer 1003 is formed thereon. This single crystal Si layer on the first Si substrate is bonded to the main face of second Si substrate 1004 with interposition of insulation layer 1005 (FIG. 17A). Then the wafer is separated at the porous layer (FIG. 17B). The bared porous Si layer on the second substrate surface is removed selectively to form a SOI substrate (FIG. 17C). First substrate 1001 can be used again after removal of the porous layer.
In the above process disclosed in Japanese Patent Application Laid-Open No. 7-302889, the substrates are separated by utilizing the brittleness of the porous silicon layer in comparison with the nonporous silicon layer, enabling reuse of the substrate used for semiconductor substrate production process, thus lower the production cost.
Japanese Patent Application Laid-Open No. 8-213645 discloses a process in which a semiconductor layer is formed, on a porous silicon layer, for a photoelectric conversion portion of a solar cell and the semiconductor layer is later separated at the porous layer to reuse the substrate having the porous silicon layer. In the process disclosed in Japanese Patent Application Laid-Open No. 8-213645, the semiconductor layer is bonded to a rigid jig with an adhesive, and the silicon substrate having the porous silicon layer is bonded to another rigid jig, and thereafter the jigs are pulled respectively in opposite directions to separate the semiconductor layer from the porous layer. In this method, the force is required for pulling the jigs to separate the entire face of the wafer in one stroke. Since the required pulling force is proportional to square of the wafer diameter, a larger wafer diameter requires a larger pulling force for the separation. Further, owing to the lower flexibility and to the difficulty in control of the force, the separation cannot easily be made at the desired region.
In production of a solar cell, the substrate for the element should be inexpensive in view of the production cost. Generally, silicon is used as the semiconductor constituting the solar cell. Single crystal silicon is most suitable from the standpoint of photoelectric conversion efficiency. However, amorphous silicon is advantageous for the larger cell area and the lower cell production cost. In recent years, polycrystalline silicon is being investigated for achieving a low production cost like the amorphous silicon, and a high energy-conversion efficiency like the single crystal silicon.
However, in the conventional methods employing single crystal silicon or polycrystal silicon, the crystal mass is sliced into substrate plates, so that the thickness of the substrate is limited to not less than 0.3 mm. This thickness is much larger than that necessary for absorbing the luminous energy sufficiently. Therefore, the material is not effectively utilized. For the lower production cost, further decrease of the thickness is desired. Recently, a method of silicon sheet formation by spinning has been disclosed in which liquid droplets of molten silicon are introduced into a mold to form a sheet. In this method, the thickness of the resulting sheet is about 0.1 to 0.2 mm, which is still thicker than the necessary and sufficient thickness (20 .mu.m to 50 .mu.m).
In another disclosure, a thin epitaxial layer, grown on a single crystal silicon substrate and separated (peeled) from the substrate, is used for the solar cell to achieve a higher energy conversion efficiency and a lower production cost (Milnes, A. G. and Feucht D. L.: "Peeled Film Technology Solar Cells", IEEE Photovoltaic Specialist Conference, p.338, 1975). In this method, an intermediate layer of SiGe is formed between the single crystal silicon as the substrate and the grown epitaxial layer, and after the heteroepitaxial growth, the grown layer is peeled by selective melting of the interlayer. However, heteroepitaxial growth is generally not advantageous in production cost because of probability of causing defects in the growth interface owing to the difference of the lattice constants, and because of the use of different materials.
U.S. Pat. No. 4,816,420 discloses a process for producing a thin crystal solar cell. In this process, a sheet-shaped crystal is formed through a mask, on a crystal substrate, by selective epitaxial growth and lateral growth, and the resulting sheet is separated from the substrate. In this method, the apertures of the mask are provided in lines, the crystal is grown by line seeding by selective epitaxial growth and lateral growth, and the crystal sheet is peeled mechanically by utilizing cleavage of the crystal. Therefore, at a size of the line seed larger than a certain limit, the larger contact area of the crystal sheet with the substrate tends to cause breakage of the crystal sheet during the peeling operation. In particular, in production of a solar cell of a larger area, this method cannot be applied practically even at the smallest aperture line width (practically about 1 .mu.m) at the line length of several millimeters to several centimeters or more.
Japanese Patent Application Laid-Open No. 6-45622 applied for by the inventors of the present invention, discloses a solar cell production process in which a porous silicon layer is formed by anodization on a surface of a silicon wafer, the porous silicon layer is peeled and is fixed onto a metal substrate, and an epitaxial layer is formed on the porous layer to obtain a thin film crystal solar cell having excellent properties. However, this method is not satisfactory since the metal substrate is treated at a high temperature, and the epitaxial layer can be contaminated with impurities.
Japanese Patent Application Laid-Open No. 5-211128 discloses another process for separation of a substrate by use of a bubble layer which is different from the aforementioned porous layer, but has a function similar thereto. In this process, a bubble layer is formed in a silicon substrate by ion implantation. Crystal rearrangement and bubble coalescence are caused in the bubble layer by heat treatment, and the surface region of the silicon substrate (called a thin semiconductor film) is stripped off at the bubble layer. The thin semiconductor film in this disclosure means an outermost region of a bulk Si where no or few implanted ions are present.
This process, however, should be conducted at a temperature where the crystal rearrangement and the bubble coalescence occur effectively. It is not easy to establish the ion implantation conditions and to optimize the heat treatment of this process.